1. Technical Field
This disclosure relates to a semiconductor memory device, and more particularly, to a method of controlling refresh operation in multi port dynamic random access memory (DRAM) and a memory system using the method.
2. Description of the Related Art
DRAM devices have been widely used because of their high integration density and high operating speed. A DRAM cell includes a transistor and a capacitor. A considerable number of such DRAM cells can be integrated into a single DRAM device. DRAM cells are smaller than other memory cells such as static random access memory (SRAM) cells.
Due to leakage current, however, the electrical charge of DRAM cells decreases over time after the DRAM cells are charged. As a result, DRAM cells need to be periodically refreshed. Specifically, data stored in the capacitors of the DRAM cells need to be refreshed periodically.
There are two methods of refreshing DRAMs: an auto-refresh method and a self-refresh method. In the auto-refresh method, a predetermined time period is allocated within a normal operating period of a DRAM during which a refresh operation is automatically performed. In the self-refresh method, a refresh operation is performed when a DRAM is in a standby mode. The auto-refresh method and the self-refresh method are obvious to one of ordinary skill in the art to which semiconductor memory devices pertain.
Dual-port RAMs are memories having two input/output ports. Specifically, dual-port RAMs have one input/output port for allowing access to the dual-port RAMs by associated processors and one input/output port for allowing access to the dual-port RAMs by external processors via buses. Thus, data stored in a dual-port DRAM can be accessed via 2 ports.
Dual-port RAMs may be classified into dual-port DRAMs having DRAM cells as unit memory cells and dual-port SRAMs having SRAM cells as unit memory cells. In dual-port SRAMs, each of the unit memory cells, which can store 1-bit data, includes 4 transistors forming a latch structure and 2 transistors forming a transmission gate. In typical SRAMs, data is stored in each unit memory cell using the latch structure, and thus, there is no need to perform a refresh operation to preserve the data. However, since an SRAM cell includes 6 transistors, it occupies a larger area than a DRAM cell with 1 transistor and 1 capacitor.
Dual-port DRAMs, unlike dual-port SRAMs, need to have their unit memory cells refreshed periodically.
FIG. 1 is a block diagram of a conventional dual-port DRAM 10 which can be accessed by 2 processors. Referring to FIG. 1, the dual-port DRAM 10 includes 4 memory banks A, B, C, and D. A first processor 12 can access the memory banks A, B, and C, and a second processor 14 can access the memory banks C and D.
The memory bank C is shared by the first and second processors 12 and 14. Thus, the memory cells in the memory bank C can be refreshed independently by the first and second processors 12 and 14.
An auto-refresh command is prioritized above all other commands, and is thus applied to a DRAM ahead of the other commands. However, if the second processor 14 issues a refresh command while a refresh operation is performed in response to a refresh command issued by the first processor 12, the refresh command issued by the second processor 14 may not be executed until the refresh operation performed in response to the refresh command issued by the first processor 12 is complete. In this case, even if the second processor 14 issues another command, it cannot be executed until the refresh command issued by the second processor 14 is executed.
In addition, if a refresh command is issued by the second processor 14 after the refresh operation performed in response to the refresh command issued by the first processor 12 is complete, the power consumption of the dual-port DRAM 10 undesirably increases due to the repetition of the auto-refresh operation.